(1) Field of the Invention
The present invention relates generally to semiconductor integrated circuit technology and more particularly to memory cells used in split gate flash EEPROMs (Electrically Erasable Programmable Read Only Memory).
(2) Description of Prior Art
In programming and erase operations used in split-gate flash memory cells, electrons are transferred into (programming) or out of (erasing) floating gates. As is well known in the art, this transfer of electrons is accomplished by tunneling through thin insulator layers separating the three basic components of a split-gate memory cell, namely: substrate, floating gate and control gate. The programming and erase operations are affected by the passage of electrons trough the intervening thin insulator layers by application of different voltage levels to the control gate and source and drain of the cell. It is important that no extraneous current paths exist that could interfere with the charge transfers of the programming and erasing operations. Such extraneous current paths can seriously impact device yield and reliability and steps need be taken to prevent the occurrence of extraneous current paths.
A common and persistent defect found in conventional split gate flash cells is shown in FIGS. 1a and 1b. This defect is appropriately denoted “poly tip” and it is what gives rise to an extraneous current that is commonly called “reverse tunneling”. Shown in FIG. 1a is a typical structure for a conventional split gate flash cell. A floating gate, 6, is disposed over a gate oxide layer, 4, which had been formed over a silicon region, 2. A thermally grown poly oxide layer, 10, is disposed over the floating gate and an intergate insulator layer, 8, is deposited over the poly oxide layer, the floating gate sidewalls and the exposed gate oxide layer. A magnified view of the region where the poly tip occurs is shown in FIG. 1b. An etching of the poly layer and a wet dip, process steps used to form the floating gate, can give rise to an undercut, 14, of the floating gate. The undercut is replicated on the deposited intergate insulator layer, as shown in FIG. 1b. Another method of separating the control gate from the floating gate is to grow an oxide layer over the floating gate sidewalls, but the replication of the undercut would also occur in this method. In either method, when forming the control gate, 12, the undercut shape is filled with conductive material giving rise to a poly tip, 16.
Since the poly tip is a feature that causes reverse tunneling, it is important to devise split gate structures and processing methods that do not produce a poly tip. Prior art methods exist that produce structures that do not contain a poly tip or in which the affect of the poly tip is alleviated. This is usually accomplished by increasing the spacing between the control gate and the bottom of the floating gate, which can be done in various ways, such as, tapering the sides of the floating gate or by forming insulating barriers and spacers. These methods invariably involve extra processing steps and adding processing steps is inherently undesirable because of increased cost and decreased reliability. Moreover other problems could be introduced. For example, silicon nitride spacers could be used to alleviate the poly tip problem, but such spacers could give rise to undesirable excessive stress and the high nitride deposition temperature strains the present generation thermal budget limitations.
Chiang et al. U.S. Pat. No. 6,617,638 discloses a method of forming a split-gate flash memory cell with a tapered floating gate. The negatively tapered walls provide a geometry better suited for forming thicker spacers around the floating gate. Hsieh et al. U.S. Pat. No. 6,465,841 teaches a method to fabricate a split-gate flash memory cell with nitride spacers. U.S. Pat. No. 6,380,030 to Chen et al. shows an implant method for forming a silicon nitride spacer. U.S. Pat. No. 6,031,264 to Chien et al. discloses a nitride spacer for flash EPROM.